Since the development of integrated circuit technology, computers and computer storage devices have been made from wafers of semiconductor material comprising a plurality of integrated circuits. After a wafer is made, the circuits are typically separated from each other by dicing the wafer into small chips. Thereafter, the individual chips are bonded to carriers of various types, interconnected by wires and are packaged. Such "two-dimensional" packages of chips fail to optimize the number of circuits that may be fabricated in a given space, and introduce undesirable signal delays, capacitance, and inductance as signals travel between chips.
Recently, three-dimensional arrays of chips have emerged as an important packaging approach. A typical multichip electronic module consists of multiple IC chips adhesively secured together as a monolithic structure. A metallization pattern is often provided directly on one (or more) side surface(s) of the module for IC chip interconnections and for electrical connection of IC chips to circuitry external to the module. The metallization pattern can include both individual contacts and bussed contacts. Multichip modules comprising stacks of IC chips are referred to herein as "stacks."
The current stack fabrication process suffers from problems that negatively affect overall stack manufacturing yield and efficiency. As a result, stack manufacturing costs remain high and profit margins remain low. Several of these problems involve: (1) IC chips becoming unusable in stacks due to edge chipping during wafer dicing; (2) difficult side-surface channel via fabrication; (3) side-surface polyimide edge bead thickness; and (4) variable T-connect quality. Each of these problems is discussed in further detail hereinbelow.
Edge Chipping
It is important to have very uniform edges on IC chips used in a stack. When IC chips are laminated into a stack, the edges of the IC chips define the stack's side-surface on which thin-film metal, necessary for chip interconnection, is deposited. To control defects, this thin-film processing requires a defect-free stack side-surface. Therefore, chip edge defects directly impact the ability to build the stack side-surface thin-film structures.
IC chip edge chipping results from conventional mechanical wafer dicing (i.e., sawing or laser cutting) through a thick polyimide layer and silicon substrate. As one prior solution, the wafer dicing process was operated at 1/10th the typical dicing rate to minimize IC chip edge defects. This approach has met with minimal success as IC chip edge chipping still occurs. Furthermore, besides the extremely slow dicing rates employed, there is an expensive and time-consuming post dicing chip edge inspection process. The net yield of this conventional dicing process is unpredictable and ranges from, for example, 30 to 90%.
Channel Via Fabrication
T-connects are used to provide an electrical interface between each IC chip in a stack and the wiring on the stack side-surface. More specifically, the T-connects join transfer metal leads that extend from the electrical contacts on the surfaces of the IC chips to the edges of the IC chips that correspond to the side-surfaces of the stack. The current process for forming a T-Connect on the side-surface of the stack entails wet etching a channel via through a polyimide passivation layer disposed on the side-surface. This via must be accurately aligned, within a few microns, to the transfer metal leads extending to the edge of an IC chip and accordingly presented to the side-surface of the stack.
Due to the irregular IC chip sizes that result from conventional dicing processes, the alignment of the IC chips within the stack is such that the channel via etch must be individually performed for each chip in the stack (i.e., in a step and repeat fashion). The channel via alignment is critical because any misalignment results in an electrical short between the T-Connect pads and the grounded silicon substrate. Misaligned channel vias are detected in a post polyimide etch inspection process that further increasing stack build costs. If problems are detected, rework requires repolishing the side-surface of the stack which is yet another time-consuming and difficult process. Further, only a few side-surface reworks can be performed before the entire stack must be discarded. The critical alignment of channel vias is further complicated by the lack of alignment marks on the side-surface of the stack.
As a further problem, the stack side-surface polyimide layer is relatively thin, currently, for example, approximately 2 um. This facilitates etching the channel vias within the required tolerance. However, the thinness of the side-surface polyimide layer makes it more susceptible to stack side-surface defects including, for example, defect laden IC chip edges, polishing defects, contamination, etc. Thus, the chances for having a hole/defect in the polyimide which could result in an electrical short between a T-Connect pad and the silicon IC chip edge are increased.
Edge Bead
When the stack side-surface polyimide layer discussed above is applied, significant perimeter edge beads usually occur. These edge beads are large in both height and lateral dimensions. For example, edge beads can have heights 2-3 times (or greater) than the thickness of the applied polymeric layer and a lateral dimension of 500-1,000 um.
To adequately form (i.e., etch) the channel vias within the tight tolerance discussed above, the thickness of the side-surface polyimide layer must be uniform. If the thickness is not uniform due to edge beading, then the etch pattern will not meet the channel via tolerance. For example, nonuniform side-surface polyimide layer thickness results in a nonuniform channel via size. Certain parts of the channel via will be too small (i.e., not sufficiently removed), while other areas will be too large. The former results in polyimide being left over the end of the transfer metallurgy line and the inability to form an electrically conductive T-Connect, while the latter results in exposure of the silicon chip edge and an electrical short between the T-Connect pad and the silicon chip. In addition to the impact on the channel via formation, the large height variation of the edge bead precludes the formation of thin-film metallization features which require photolithographic definition, (e.g., stack side-surface wiring and T-Connect pads).
The current technique employed to avoid these problems is to "ground rule out" the edge bead area on the stack side-surface. This involves identification of the edge-bead area around the perimeter of the stack side-surface in which no photolithographic features (e.g., channel via or thin-film wiring/T-Connect pads) can be fabricated. Because an extensive area of the stack side-surface becomes unavailable, there is a decrease in the stack side-surface wiring density.
T-Connect Quality
Formation of an electrically good T-Connect depends upon the quality and cleanliness of the end of the transfer metal lead presented to the stack side-surface. It has been shown that stack side-surface polishing deposits material (e.g., polyimide flakes, polishing media and contaminants) on the end of the transfer metal lead such that the T-Connect electrical resistance/conductivity varies. Typical resistance may range from a complete open to a few ohms. Unfortunately, this contamination is unpredictable and cannot be easily visually detected (to date, only a Scanning Electron Microscope has been used to view the contamination). Therefore, one does not know whether there will be a T-Connect resistance problem on a specific stack until after the T-Connects have been deposited and a parametric electrical test performed. If a problem is found, the entire stack side-surface has to be reworked. As discussed hereinabove, there is a limit to the number of side-surface reworks possible before the entire stack must be discarded.
Beyond the problems discussed above, the current stack fabrication process requires much tighter dicing tolerance than is currently required for IC chip dicing associated with single IC chip, plastic encapsulation type packaging. The dicing tolerance for plastic packaging is approximately, for example, +/-20 um, while the stack process requires a dicing tolerance of approximately, for example, +/-5 um.
When IC chips of inadequate tolerance are stacked and laminated, the varying IC chip sizes result in IC chips shifting within the stack. Such shifting causes misalignment of, for example, the transfer metal leads of each IC chip in the stack. Accordingly, the side-surface of the stack requires polishing to expose all of the transfer metal leads, thereby reducing the total number of times that the stack side-surface. can be reworked. Furthermore, the misalignment of the IC chips results in wider side-surface wiring being required to `capture` all the side-surface connections. Side-surface wiring density is therefore reduced.
As yet another problem, the varying IC chip sizes force the stack/lamination fixture used for assembly of the stack to be large enough to accommodate IC chips of varying sizes up to the maximum specification limit. This increases the opportunity for IC chip shifting. Moreover, the forces on the stack during lamination are concentrated on the largest chips in the stack because they are in direct contact with the lamination fixture. Therefore, these large chips tend to become damaged during lamination. This further compromises stack yield and requires increased side-surface polishing.
The present invention is directed toward solutions to the above discussed problems.